A new chip architecture from IBM can integrate nearly 100 billion transistors into a chip the size of a human fingernail, nearly double the transistor density of the company’s previous generation of chip technology. The resulting improvement in chip computing performance and power efficiency comes from what IBM describes as the “world’s first sub-1 nanometer chip technology” for AI data centers.
“It’s not just an incremental step, it’s a significant leap forward,” Jay Gambetta, director of IBM Research and an IBM Fellow, said at an early news conference. He described the new chip technology as “pointing to a future in which computing will become significantly more powerful without a corresponding increase in power.”
It’s worth unraveling what “the world’s first sub-1 nanometer chip technology” means, because it’s not practical to build reliable functional chips with transistors and other features smaller than 1 nanometer due to various physical limitations. Instead, IBM is basically claiming that its new “nanostack” architecture can deliver the computing performance improvements that would be expected if a theoretical chip could be built with physical characteristics smaller than 1 nanometer.
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